The present invention relates to a semiconductor circuit apparatus formed of a direct coupled FET logic circuit (DCFL) by using a gate having a junction type field effect transistor (J-FET).
A DCFL requires only a small number of elements for forming a gate and thus is suitable for providing a large scale logic circuit.
FIG. 1 shows an example of a conventional DCFL. In this conventional DCFL, two inverters 11 and 21 are directly coupled. The inverters 11 and 21 consist of J-FETs 12 and 22 using GaAs semiconductors and resistors 13 and 23, respectively. With this arrangement, the OFF-resistance of the J-FET 12 is normally considerably higher than the resistance of the resistor 13 so that the high level of an output voltage of the J-FET 12, i.e., an input voltage to J-FET 22, is substantially the same as the voltage (VDD) of a drive power source (not shown).
When a ring oscillator is formed by a DCFL as described above and propagation delay time (.tau.pd) per gate is measured, .tau.pd is gradually increased in accordance with the increase in the voltage VDD as shown by the solid line in FIG. 2. In constrast to this, when Schottky barrier type field effect transistors (MES-FETs) are used in place of the J-FETs 12 and 22, .tau.pd is kept constant even if the voltage VDD is increased, as shown by the dotted line in FIG. 2.
This is assumed to be caused by a carrier storage effect of a channel, or a substrate of the J-FET 22 is enhanced as the high level input voltage of the J-FET 22 which becomes higher than a forward voltage (Vf=1.0 V) at a pn junction.
Therefore, in a conventional example as mentioned above, when the voltage VDD is set to be, e.g., higher than 1.5 V, .tau.pd as well as power consumption will be increased, resulting in a great disadvantage.
For this reason, the voltage VDD must be set in a range of, e.g., 1.0 to 1.4 V, and the setting condition of the voltage VDD becomes critical. In addition, in some J-FETs, the voltage VDD rapidly increases from the vicinity of 1.2 V, depending upon a condition of the substrate. In this case, the setting condition of the voltage VDD becomes more strict. In other words, only a small margin against variation in the voltage VDD is allowable, this resulting in difficult circuit design.